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| − | This is a list of several MD hardware quirks that don't exactly fit in any other categories.
| + | #REDIRECT [[sega:SCHG:Mega Drive Quirks]] |
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| − | ==CLR on VDP data port==
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| − | If the VDP is set to VRAM/CRAM/VSRAM Write, using the clr instruction on the VDP data port will result in a system crash:
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| − | <asm>clr.w $C00000</asm>
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| − | This is because the clr instruction is treated as a Read-Modify-Write instruction on the MC68000 and MC68008 CPUs. The CPU first attempts to read the value located at $C00000, but the VDP's in data write mode, so the system hangs. This was fixed in the MC68010 CPU, which does not read the address before writing 0.
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| − | * Emulators that implement this quirk: '''Unknown'''
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| − | ==TAS instruction support==
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| − | The MC68000 has an instruction, TAS (test-and-set), that is used for synchronizing multiple MC68000s in a multi-CPU system. The TAS instruction uses a different bus cycle than other instructions, and isn't supported by either the MD1 or MD2 hardware. However, the Majesco Genesis 3 does support TAS, which breaks a few games that incorrectly use the TAS instruction.
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| − | * Emulators that do not implement TAS: Probably all.
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| − | * Emulators that do implement TAS: '''Unknown'''
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| − | {{SCHGuides}}
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| − | [[Category:Sonic Community Hacking Guide]] | |
