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SCHG:VDP Documentation/General/Registers

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SCHG: VDP Documentation
Main Article
General
General Information
Ports
Control port
Getting VDP status
Writing to registers
Setting VDP access
Data port
H/V counter
Registers
Direct Memory Access
Interrupts
Vertical interrupt
Horizontal interrupt
External interrupt
Memory
Memory Divisions
Video RAM
Horizontal scroll table
Sprite attribute table
Plane name tables
Color RAM
Vertical Scroll RAM
Formats
Data Formats
Patterns
Palettes
Display
Display Control
Scroll planes
Window plane
Sprites
Priority
Interlace
Shadow and highlight
Bugs
VDP Bugs
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This article is a work in progress.
Its content and location may change completely and frequently until this notice is removed.


Contents

$00 - Mode Set Register No. 1

Bit Name Description
7 -- No effect
6
5
4 IE1 Horizontal interrupt enable

When set, horizontal interrupts will be generated.

3 -- Invalid when set
2 -- Palette select

When clear, only bit 1 of each nybble in a CRAM palette entry is used, giving 8 available colors.

When set, bits 1, 2 and 3 of each nybble are used, giving 512 available colors.

1 M3 HV counter latch enable

When set, the HV counter will be latched when a level 2 interrupt is generated. The HV counter will resume normal operation when this bit is cleared. (untested, need more info)

0 -- Display disable

Setting this bit actually turns off all display generation, as opposed to the screen blanking feature which simply shows the backdrop color.

$01 - Mode Set Register No. 2

Bit Name Description
7 -- TMS9918 display select

When set, the display is put in a TMS9918-like state, similar to one of it's text display modes. Each 8x8 block is filled with a solid color from the palette, and has no pattern data. The sprites seem to be active. I couldn't select any of the other TMS9918 modes through the usual TMS9918 mode bits. It would appear all the colors are actually affected by CRAM, instead of using a fixed color set.

6 DISP Display Enable

When cleared, the display is blanked. Any line that is blanked is filled with the backdrop color. During this time, you can freely access VDP memory with no limitations on the number of writes per line.

5 IE0 Vertical Interrupt Enable

When set, vertical interrupts will be generated.

4 M1 DMA Enable

When set, DMA operations will be enabled. Otherwise, DMA commands will be ignored by the VDP.

3 M2 Output format

Selects between a PAL (240) and NTSC (224 lines) display.

2 -- SMS display select

Toggles between the Master System (mode 4) and Genesis (mode 5) display modes. While in mode 4, none of the registers which normally affect the Genesis work; and the unused registers (8, 9 - can't test 6) now function. The mode bits which select TMS9918 modes on a real SMS have no function here. (This is why the SMS game F16 Fighter will not work with a Power Base Converter, it uses some of the TMS9918 modes in-game).

The one exception is register $0C. You can set up a 320x192 display, but the leftmost eight columns read 'garbage' data for the name table attributes. Enabling interlace makes the display unstable. (and this is partially true for a 320x192 picture, which shakes slightly) I'd advise you set $0C to zero to enable a 256x192 display, which is the normal SMS resolution. The Genesis always generates a 224 line picture; the 192 lines in SMS mode are centered in the middle of the screen.

I could not get the top row or right column lock features to work while in SMS mode. Apart from this bit, the M3 pin on the cartridge connector also puts the machine into SMS mode, which may fully enable all video features.

1 -- No effect
0 -- This bit has an interesting effect; horizontal scrolling is disabled, and it would almost seem like the horizontal scroll value modifies the horizontal retrace / blanking / sync start and end positions around; the middle of the display is blanked out, and will scroll left or right. (note the blanked area scrolls - not the background) Moving too far in one direction, so the blanked area is offscreen, totally corrupts the display.

Combining bits 7 (TMS9918 mode) and 2 (SMS mode) has no effect.

$02 - Pattern Name Table Address for Scroll A

Bits 5-3 of this register correspond to bits A15-A13 of the name table address for plane A.

$03 - Pattern Name Table Address for Window

Bits 5-1 of this register correspond to bits A15-A11 of the name table address for the window.

In 40-cell mode, A11 is always forced to zero.

$04 - Pattern Name Table Address for Scroll B

Bits 2-0 of this register correspond to bits A15-A13 of the name table address for plane B.

$05 - Sprite Attribute Table Base Address

Bits 6-0 of this register correspond to bits A15-A09 of the sprite attribute table.

In 40-cell mode, A09 is always forced to zero.

$07 - Backdrop Color

Bits 5-0 of this register select a palette entry to be used as the backdrop color.

The backdrop color is displayed in the following places:

  • The overscan area around the physical display
  • Any line where the display enable bit has been cleared
  • Any pixel which is transparent in all planes and sprites intersecting it

Note that even though the first palette entry on each row cannot be used by any patterns, these entries can be used for the backdrop color.

$0A - H Interrupt Register

Bits 7-0 specify the value to be loaded in the counter; for complete details see the "Interrupts" section.

$0B - Mode Set Register No. 3

Bit Name Description
7 -- No effect
6
5
4
3 IE2 When set, external interrupts will be enabled, caused by the TH pin being set to input mode and having the TH interrupt enable bit set. (Both of these are controlled by the Genesis' I/O registers)
2 VSCR When clear, full screen vertical scrolling is used. When set, 2-cell column based vertical scrolling is used.
1 HSCR Determines how the horizontal scroll table will be interpreted. 0 = full screen scroll, 1 = line scroll, 2 = cell scroll and 3 = line scroll again.
0 LSCR

$0C - Mode Set Register No. 4

Bit Name Description
7 RS0 See RS1.
6 -- No effect
5 -- Seems to affect the display mode in the same way as setting RS to 1.
4 -- No effect
3 S/TE Enable Shadow/Highlight Mode.
2 LSM1 Controls interlacing. 0 = no interlace, 1 = normal resolution interlace, 2 = no interlace again and 3 = double resolution interlace. Changes do not take effect until the next horizontal blank.
1 LSM0
0 RS1 Controls horizontal resolution together with RS0. 0 = 32 cell mode, 1 = distorted 40 cell mode, 2 = invalid and 3 = 40 cell mode.

$0D - H Scroll Data Table Base Address

Bits 5-0 of this register correspond to bits A15-A10 of the horizontal scroll data table address.

$0F - Auto Increment Data

Bits 7-0 specify the value to be added to the VDP's address register after every read or write to the data port.

A setting of zero means the address register is not incremented.

$10 - Scroll Size

Bit Name Description
7 -- No effect
6
5 VSZ1 Controls the vertical size of the name tables for planes A and B. 0 = 32 cells, 1 = 64 cells, 2 = invalid and 3 = 128 cells.
4 VSZ0
3 -- No effect
2
1 HSZ1 Controls the horizontal size of the name tables for planes A and B, using the same values as VSZ. If this is set to 2, the first row of the name table will be shown for every line of the display.
0 HSZ0

$11 - Window H Position

Bit Name Description
7 RIGT See below
6 -- No effect
5
4 WHP5 See below
3 WHP4
2 WHP3
1 WHP2
0 WHP1


This register will affect the window shown on the current line, if the current line does not fall into the vertical range specified by register $12.

The WHP field defines the horizontal range of the window, in units of two cells (16 pixels).

Setting the WHP field to zero disables the window. Any nonzero value indicates how many 2-cell columns wide the window plane is (0=no window, 1=2 cells, 2=4 cells, 3=6 cells, etc.).

When RIGT=0, the window is shown from column zero to the column specified by the WHP field. For instance, if RIGT=0 and WHP=4, the window is displayed on columns zero up to (and including) column seven.

When RIGT=1, the window is shown from the column specified in the WHP field up to the last column in the display meaning column 31 or 39 depending on the screen width setting. For instance, if RIGT=1 and WHP=4, the window is displayed on columns eight up to (and including) column 31 or 39.

Having WHP set to zero and RIGT=1 is a legal setting; it means the window is shown from column zero up to the last column in the display, meaning the entire line is taken up by the window plane.

There is a bug in the window processing. This occurs when the window is showing partially on the left side of the screen, specifically when the VDP is drawing the 2-cell column from plane A that immediately proceeds the last column the window was drawn on (i.e. WHP+1).

If the lower four bits of the horizontal scroll value for the current scan line are zero, then the name table attribute data for the current column are fetched correctly.

If the lower four bits of the horizontal scroll value for the current scan line are nonzero, the name table attribute data are fetched from next column (WHP+2).

In effect, you'll have N columns of the window plane, 1 column that has identical patterns as the next column, then the remainder of the display is drawn correctly.

Here's a diagram to illustrate this:

w   = window tiles
abc = tile columns

D3-D0 of scroll value == 0
wwwwwwwwwwwwwwwwaabbccddeeffgghh

D3-D0 of scroll value != 0
wwwwwwwwwwwwwwwwbbbbccddeeffgghh

This register can be modified with changes taking effect immediately at any point in the display frame.

Plane A is not shown in any column where plane W is shown; they cannot overlap.

$12 - Window V Position

Bit Name Description
7 DOWN See below
6 -- No effect
5
4 WVP4 See below
3 WVP3
2 WVP2
1 WVP1
0 WVP0

If the current scanline does not fall within the range specified by register $12, then register $11 determines where the window is shown for the remainder of the display.

The WVP field defines the vertical range of the window, in units of eight lines.

Setting the WVP field to zero disables the window. Any nonzero value indicates a vertical range for the window to appear in. (0=no window, 1=lines 0-$7, 2= lines 0-$F, 3= lines 0-$17, etc.)

When DOWN=0, the window is shown from line zero to the line specified by the WVP field.

For instance, if DOWN=0 and WVP=4, the window is displayed on lines zero up to (and including) line $1F.

When DOWN=1, the window is shown from the line specified in the WVP field up to the last line in the display.

For instance, if DOWN=1 and WVP=4, the window is displayed on lines $1F up to (and including) the last line in the display.

Having WVP set to zero and DOWN=1 is a legal setting; it means the window is shown from line zero up to the last line in the display, meaning the entire screen is taken up by the window plane.

Plane A is not shown in any line where plane W is shown; they cannot overlap.

$13 - DMA Length Counter Low

7 6 5 4 3 2 1 0
LG7 LG6 LG5 LG4 LG3 LG2 LG1 LG0

This is the low byte for the DMA length counter. If you wanted to transfer $1234 words using DMA, you would write $34 to this register.

$14 - DMA Length Counter High

7 6 5 4 3 2 1 0
LG15 LG14 LG13 LG12 LG11 LG10 LG9 LG8

This is the high byte for the DMA length counter. If you wanted to transfer $1234 words using DMA, you would write $12 to this register.

$15 - DMA Source Address Low

7 6 5 4 3 2 1 0
SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1

This is the low byte for the DMA source address. It contains bits 1-8 of the source address. (Bit 0 is ignored, since only word transfers are allowed, and word transfers must be aligned.)

$16 - DMA Source Address Mid

7 6 5 4 3 2 1 0
SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9

This is the middle byte for the DMA source address. It contains bits 9-16 of the source address.

$17 - DMA Source Address High

7 6 5 4 3 2 1 0
DMD1 DMD0 SA22 SA21 SA20 SA19 SA18 SA17

This is the high byte for the DMA source address. It contains bits 17-22 of the source address, plus two DMA mode bits.

DMD1 DMD0 Description
0 SA23 68K RAM to VRAM copy. (SA23 is bit 23 of the source address.)
1 0 VRAM fill.
1 1 VRAM to VRAM copy.